//Jeff Szcinski & KQBright
//Lab 2
//ECEN 4243
//Spring 2014

module regFile (Aselect, Bselect, Dselect, abus, bbus, dbus, clk);
	input Aselect, Bselect, Dselect, dbus;
	input clk;
	output abus, bbus;
	wire aTriStateOut, bTriStateOut;
	
	/*FlipFlop0 flip0(
		.busIn(dbus[0]),
		.selectIn(clk & Dselect[0]),
		.aTriStateOut(aTriStateOut[0]),
		.bTriStateOut(bTriStateOut[0])
	);*/
	
	FlipFlop [31:0] flip(
		.busIn(dbus),
		.selectIn(Dselect),
		.clk(clk),
		.aTriStateOut(aTriStateOut),
		.bTriStateOut(bTriStateOut)
	);